1. Field of Art
This disclosure relates generally to branch cache architecture implemented in a configurable processing device.
2. Description of the Related Art
Factors such as the frequency with which information is retrieved from memory and the number of cycles to execute program elements make power consumption a constraint on processor operation. Additionally, latency caused by a number of cycles to fetch instructions from memory and look-up instructions in memory further constrains processor operation. Branch prediction improves performance by fetching instructions in advance, based on a prediction of which instructions are executed by a program.